This application claims the priority benefit of Taiwan application serial no. 89113005, filed Jun. 30, 2000.
1. Field of the Invention
The present invention relates to a layout. More specifically, it is related to an array-type layout for silicon on insulator (SOI) transistor.
2. Description of the Related Art
Silicon on Insulator (SOI) has been so well known as a new technique. Compared to devices formed on the bulk wafer, devices formed on the (SOI) exhibit enhanced capabilities, such as low power consumption, low threshold operation and high performance.
Generally, the Silicon on Insulator lies within the wafer not far from the wafer surface and separates from the surface of the main body of the substrate. Utilizing of the wafer with SOI can help reduce latch up associated with complementary metal oxide semi-conductors (CMOS), and thus reduce the occurrence of soft error. Moreover, the wafer with SOI can raise the operational speed of the integrated circuit.
Conventional large-area diode layout usually uses finger-type layout. For SOI devices, because of the existence of a buried oxide and the application of a shallow trench isolation, difficulty in thermal dissipation encounters. As future devices become increasingly smaller, improving the effective conduction area of the devices and improving thermal dissipation and performance of the devices are important issues.
FIG. 1 is a top view of a conventional large-area SOI NMOS transistor. The layout used in FIG. 1 is a finger-like layout.
As shown in FIG. 1, a polysilicon gate structure 12 is arranged on a P+ body contact region 10. Between the polysilicon gate 12, a finger-like array of alternating N+ source region 14 and N+ drain region 16 of the second conductive type is arranged in the P+ body contact region 10.
As the schematic view of illustration 1 depicts, the width of each polysilicon gate structure 12 is W. If the operation is turned on in a uniform manner, and there are m columns, then the line width of the effective conduction area is Weff=(mxe2x88x921)W.
An array-type layout for a silicon on insulator (SOI) transistor. A body contact region of the first conductive type is provided. A polysilicon gate structure is arranged in array over the body contact region. The polysilicon gate structure divides the body contact region into an array of alternating source regions of a second conductive type and drain regions of a second conductive type.
This invention is not only capable of increasing the effective conduction area of this device despite surface area limitations, it is also able to improve the performance and thermal dissipation of this device.
This invention increases the effective conduction area of conventional (SOI) devices given the present constraints on size. Furthermore, it also improves the thermal dissipation and performance of these devices.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.